SheikahWolf/DC-Load-Analog
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UPDATE

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This commit is contained in:
SheikahakiehS 2021-04-19 17:00:35 +08:00
parent 4dcbed544d
commit b4d462519c
4 changed files with 37 additions and 272 deletions
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4
DC-Load-Analog.kicad_pcb
View File

@ -1,3 +1,4 @@
<<<<<<< HEAD
(kicad_pcb (version 20171130) (host pcbnew "(5.1.9)-1")
(general
@ -15921,3 +15922,6 @@
)
)
)
=======
(kicad_pcb (version 4) (host kicad "dummy file") )
>>>>>>> parent of 514b400 (2021.04.19_17:00_UPDATE)

259
DC-Load-Analog.pro
View File

@ -1,10 +1,29 @@
update=2021/4/19 15:14:35
update=22/05/2015 07:44:53
version=1
last_client=kicad
[general]
version=1
RootSch=
BoardNm=
[pcbnew]
version=1
LastNetListRead=
UseCmpFile=1
PadDrill=0.600000000000
PadDrillOvalY=0.600000000000
PadSizeH=1.500000000000
PadSizeV=1.500000000000
PcbTextSizeV=1.500000000000
PcbTextSizeH=1.500000000000
PcbTextThickness=0.300000000000
ModuleTextSizeV=1.000000000000
ModuleTextSizeH=1.000000000000
ModuleTextSizeThickness=0.150000000000
SolderMaskClearance=0.000000000000
SolderMaskMinWidth=0.000000000000
DrawSegmentWidth=0.200000000000
BoardOutlineThickness=0.100000000000
ModuleOutlineThickness=0.150000000000
[cvpcb]
version=1
NetIExt=net
@ -12,241 +31,3 @@ NetIExt=net
version=1
LibDir=
[eeschema/libraries]
[pcbnew]
version=1
PageLayoutDescrFile=
LastNetListRead=
CopperLayerCount=2
BoardThickness=1.6
AllowMicroVias=0
AllowBlindVias=0
RequireCourtyardDefinitions=0
ProhibitOverlappingCourtyards=1
MinTrackWidth=0.2
MinViaDiameter=0.4
MinViaDrill=0.3
MinMicroViaDiameter=0.2
MinMicroViaDrill=0.09999999999999999
MinHoleToHole=0.25
TrackWidth1=0.25
TrackWidth2=0.254
TrackWidth3=0.381
TrackWidth4=0.508
TrackWidth5=0.762
TrackWidth6=1.27
TrackWidth7=2.54
TrackWidth8=5.08
TrackWidth9=7.62
ViaDiameter1=0.8
ViaDrill1=0.4
ViaDiameter2=0.635
ViaDrill2=0.3048
ViaDiameter3=1.27
ViaDrill3=0.6096
ViaDiameter4=2.54
ViaDrill4=1.2192
dPairWidth1=0.2
dPairGap1=0.25
dPairViaGap1=0.25
SilkLineWidth=0.12
SilkTextSizeV=1
SilkTextSizeH=1
SilkTextSizeThickness=0.15
SilkTextItalic=0
SilkTextUpright=1
CopperLineWidth=0.2
CopperTextSizeV=1.5
CopperTextSizeH=1.5
CopperTextThickness=0.3
CopperTextItalic=0
CopperTextUpright=1
EdgeCutLineWidth=0.05
CourtyardLineWidth=0.05
OthersLineWidth=0.15
OthersTextSizeV=1
OthersTextSizeH=1
OthersTextSizeThickness=0.15
OthersTextItalic=0
OthersTextUpright=1
SolderMaskClearance=0
SolderMaskMinWidth=0
SolderPasteClearance=0
SolderPasteRatio=-0
[pcbnew/Layer.F.Cu]
Name=F.Cu
Type=0
Enabled=1
[pcbnew/Layer.In1.Cu]
Name=In1.Cu
Type=0
Enabled=0
[pcbnew/Layer.In2.Cu]
Name=In2.Cu
Type=0
Enabled=0
[pcbnew/Layer.In3.Cu]
Name=In3.Cu
Type=0
Enabled=0
[pcbnew/Layer.In4.Cu]
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Type=0
Enabled=0
[pcbnew/Layer.In5.Cu]
Name=In5.Cu
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Enabled=0
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Enabled=0
[pcbnew/Layer.In8.Cu]
Name=In8.Cu
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[pcbnew/Layer.In9.Cu]
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Type=0
Enabled=0
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Name=In10.Cu
Type=0
Enabled=0
[pcbnew/Layer.In11.Cu]
Name=In11.Cu
Type=0
Enabled=0
[pcbnew/Layer.In12.Cu]
Name=In12.Cu
Type=0
Enabled=0
[pcbnew/Layer.In13.Cu]
Name=In13.Cu
Type=0
Enabled=0
[pcbnew/Layer.In14.Cu]
Name=In14.Cu
Type=0
Enabled=0
[pcbnew/Layer.In15.Cu]
Name=In15.Cu
Type=0
Enabled=0
[pcbnew/Layer.In16.Cu]
Name=In16.Cu
Type=0
Enabled=0
[pcbnew/Layer.In17.Cu]
Name=In17.Cu
Type=0
Enabled=0
[pcbnew/Layer.In18.Cu]
Name=In18.Cu
Type=0
Enabled=0
[pcbnew/Layer.In19.Cu]
Name=In19.Cu
Type=0
Enabled=0
[pcbnew/Layer.In20.Cu]
Name=In20.Cu
Type=0
Enabled=0
[pcbnew/Layer.In21.Cu]
Name=In21.Cu
Type=0
Enabled=0
[pcbnew/Layer.In22.Cu]
Name=In22.Cu
Type=0
Enabled=0
[pcbnew/Layer.In23.Cu]
Name=In23.Cu
Type=0
Enabled=0
[pcbnew/Layer.In24.Cu]
Name=In24.Cu
Type=0
Enabled=0
[pcbnew/Layer.In25.Cu]
Name=In25.Cu
Type=0
Enabled=0
[pcbnew/Layer.In26.Cu]
Name=In26.Cu
Type=0
Enabled=0
[pcbnew/Layer.In27.Cu]
Name=In27.Cu
Type=0
Enabled=0
[pcbnew/Layer.In28.Cu]
Name=In28.Cu
Type=0
Enabled=0
[pcbnew/Layer.In29.Cu]
Name=In29.Cu
Type=0
Enabled=0
[pcbnew/Layer.In30.Cu]
Name=In30.Cu
Type=0
Enabled=0
[pcbnew/Layer.B.Cu]
Name=B.Cu
Type=0
Enabled=1
[pcbnew/Layer.B.Adhes]
Enabled=1
[pcbnew/Layer.F.Adhes]
Enabled=1
[pcbnew/Layer.B.Paste]
Enabled=1
[pcbnew/Layer.F.Paste]
Enabled=1
[pcbnew/Layer.B.SilkS]
Enabled=1
[pcbnew/Layer.F.SilkS]
Enabled=1
[pcbnew/Layer.B.Mask]
Enabled=1
[pcbnew/Layer.F.Mask]
Enabled=1
[pcbnew/Layer.Dwgs.User]
Enabled=1
[pcbnew/Layer.Cmts.User]
Enabled=1
[pcbnew/Layer.Eco1.User]
Enabled=1
[pcbnew/Layer.Eco2.User]
Enabled=1
[pcbnew/Layer.Edge.Cuts]
Enabled=1
[pcbnew/Layer.Margin]
Enabled=1
[pcbnew/Layer.B.CrtYd]
Enabled=1
[pcbnew/Layer.F.CrtYd]
Enabled=1
[pcbnew/Layer.B.Fab]
Enabled=1
[pcbnew/Layer.F.Fab]
Enabled=1
[pcbnew/Layer.Rescue]
Enabled=0
[pcbnew/Netclasses]
[pcbnew/Netclasses/Default]
Name=Default
Clearance=0.2
TrackWidth=0.25
ViaDiameter=0.8
ViaDrill=0.4
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25

32
DC-Load-Analog.sch
View File

@ -58,10 +58,10 @@ F 3 "http://www.ti.com/lit/ds/symlink/lm2904-n.pdf" H 7025 2400 50 0001 C CNN
1 0 0 -1
$EndComp
$Comp
L Device:R_POT RV1/NC
L Device:R_POT RV1/NC1
U 1 1 607A97FC
P 5275 2300
F 0 "RV1/NC" H 5600 2550 50 0000 R CNN
F 0 "RV1/NC1" H 5600 2550 50 0000 R CNN
F 1 "10K" H 5450 2475 50 0000 R CNN
F 2 "Connector_PinHeader_2.54mm:PinHeader_1x03_P2.54mm_Vertical" H 5275 2300 50 0001 C CNN
F 3 "~" H 5275 2300 50 0001 C CNN
@ -1130,10 +1130,10 @@ F 3 "~" H 9200 4800 50 0001 C CNN
1 0 0 -1
$EndComp
$Comp
L power:GND #PWR?
L power:GND #PWR0139
U 1 1 60827AB8
P 9200 5000
F 0 "#PWR?" H 9200 4750 50 0001 C CNN
F 0 "#PWR0139" H 9200 4750 50 0001 C CNN
F 1 "GND" H 9205 4827 50 0000 C CNN
F 2 "" H 9200 5000 50 0001 C CNN
F 3 "" H 9200 5000 50 0001 C CNN
@ -1154,10 +1154,10 @@ F 3 "~" H 9575 4800 50 0001 C CNN
1 0 0 -1
$EndComp
$Comp
L power:GND #PWR?
L power:GND #PWR0140
U 1 1 6082B3AB
P 9575 5000
F 0 "#PWR?" H 9575 4750 50 0001 C CNN
F 0 "#PWR0140" H 9575 4750 50 0001 C CNN
F 1 "GND" H 9580 4827 50 0000 C CNN
F 2 "" H 9575 5000 50 0001 C CNN
F 3 "" H 9575 5000 50 0001 C CNN
@ -1166,24 +1166,4 @@ F 3 "" H 9575 5000 50 0001 C CNN
$EndComp
Wire Wire Line
9575 4900 9575 5000
$Comp
L Device:R_POT RV2
U 1 1 6090B930
P 4900 2300
F 0 "RV2" H 4831 2346 50 0000 R CNN
F 1 "10K" H 4831 2255 50 0000 R CNN
F 2 "30V-3A-adjustable-regulator-:TRIM_3590S-2-103L" H 4900 2300 50 0001 C CNN
F 3 "~" H 4900 2300 50 0001 C CNN
1 4900 2300
1 0 0 -1
$EndComp
Wire Wire Line
4900 2150 5275 2150
Connection ~ 5275 2150
Wire Wire Line
5425 2300 5050 2300
Connection ~ 5425 2300
Wire Wire Line
4900 2450 5275 2450
Connection ~ 5275 2450
$EndSCHEMATC

14
DC-Load-Analog.sch-bak
View File

@ -58,10 +58,10 @@ F 3 "http://www.ti.com/lit/ds/symlink/lm2904-n.pdf" H 7025 2400 50 0001 C CNN
1 0 0 -1
$EndComp
$Comp
L Device:R_POT RV1/NC
L Device:R_POT RV1/NC1
U 1 1 607A97FC
P 5275 2300
F 0 "RV1/NC" H 5600 2550 50 0000 R CNN
F 0 "RV1/NC1" H 5600 2550 50 0000 R CNN
F 1 "10K" H 5450 2475 50 0000 R CNN
F 2 "Connector_PinHeader_2.54mm:PinHeader_1x03_P2.54mm_Vertical" H 5275 2300 50 0001 C CNN
F 3 "~" H 5275 2300 50 0001 C CNN
@ -1130,10 +1130,10 @@ F 3 "~" H 9200 4800 50 0001 C CNN
1 0 0 -1
$EndComp
$Comp
L power:GND #PWR?
L power:GND #PWR0139
U 1 1 60827AB8
P 9200 5000
F 0 "#PWR?" H 9200 4750 50 0001 C CNN
F 0 "#PWR0139" H 9200 4750 50 0001 C CNN
F 1 "GND" H 9205 4827 50 0000 C CNN
F 2 "" H 9200 5000 50 0001 C CNN
F 3 "" H 9200 5000 50 0001 C CNN
@ -1154,10 +1154,10 @@ F 3 "~" H 9575 4800 50 0001 C CNN
1 0 0 -1
$EndComp
$Comp
L power:GND #PWR?
L power:GND #PWR0140
U 1 1 6082B3AB
P 9575 5000
F 0 "#PWR?" H 9575 4750 50 0001 C CNN
F 0 "#PWR0140" H 9575 4750 50 0001 C CNN
F 1 "GND" H 9580 4827 50 0000 C CNN
F 2 "" H 9575 5000 50 0001 C CNN
F 3 "" H 9575 5000 50 0001 C CNN
@ -1172,7 +1172,7 @@ U 1 1 6090B930
P 4900 2300
F 0 "RV2" H 4831 2346 50 0000 R CNN
F 1 "10K" H 4831 2255 50 0000 R CNN
F 2 "Connector_PinHeader_2.54mm:PinHeader_1x03_P2.54mm_Vertical" H 4900 2300 50 0001 C CNN
F 2 "30V-3A-adjustable-regulator-:TRIM_3590S-2-103L" H 4900 2300 50 0001 C CNN
F 3 "~" H 4900 2300 50 0001 C CNN
1 4900 2300
1 0 0 -1